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back to boardI have no idea what's wrong...
I am using DFS (something like euler-cycle detection); checking for self-loop edges; output format is right, tho it returns little bit different for sample test:
3
3 1 2 4
4 1 2 4 3
3 2 4 3
Please, any ideas about wa#1?
oh, i forgot to add that i am doing dfs for every connected component separately!
Edited by author 15.06.2010 03:05 anyone please? I did that too,my answer is completely the same as yours,and I WA on the 1st test too |
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